Bit line and column circuitry used in a semiconductor memory

ABSTRACT

Column circuitry for a CMOS static RAM includes a bit line clamp combined with a bit line current source regulated by a voltage reference which tracks changes in transistor characteristics. Separate data read and data write lines are provided, with a differential amplifier for each pair of bit lines. The data read lines are coupled to compensated current source loads, and the differential amplifiers are couplled to switching transistors which are also compensated for transistor characteristic changes, Each bit line pair has a sneak capacitance prevention transistor so that in non-selected columns the bit line pairs are coupled together allowing the memory cells therein to pull down all of the bit lines. This isolates the read lines from unwanted capacitance in the differential amplifiers of each of the non-selected columns, Further, a VCC protection circuit is provided.

This is a continuation-in-part of Ser. No. 534,484 filed Sep. 21, 1983,now abandoned, whose disclosure is hereby incorporated by reference.

BACKGROUND OF THE INVENTION

The present invention is converned with improving the access time tomemory cells in a random access memory. The preferred embodimentdescribed herein deals with circuitry implemented on a 64K CMOS staticRAM.

Some of the delays in reading a memory cell in a static RAM comprise thecell-select time which corresponds to the time required to operate theaddress buffer and decoder followed by the word line delay. A subsequentdelay is the cell-read time which corresponds to the time required forthe sense amplifier and output buffer operation. In a 16K static RAM,the cell select time as defined is about 68% of the total delay and thecell-read time is the remaining 32%.

As static RAM density is increased, the cell-read time has become alarger percentage of the total access time. Considering a 64K staticRAM, the cell-select time is about 58% and the cell-read time is about42% of the total. Reasons for this increased percentage of total delayattributed to the cell-read time are that the bit line signal isreduceed due to weaker memory cell transistors and there is a larger bitline capacitance.

The principal object of the present invention is to reduce the cell-readtime.

SUMMARY OF THE INVENTION

The foregoing object is achieved by adding bit line loading which in thepreferred embodiment comprises a combination of a compensated currentsource to increase the bit line signal and a clamp device for insuringcell stability. Column sense amplifiers according to various aspects ofthe invention use switched compensated current sources to maximize gainand improve data line level stability. Separate read and write datapaths are added. Sneak capacitance reduction means reduces capacitancedue to non-selected columns.

BRIEF DESCRIPTION OF THE DRAWINGS

In describing the preferred embodiment, reference will be made to theaccompanying drwings wherein:

FIG. 1 illustrates bit line circuitry and some of the improved columncircuitry including column read and write circuitry with a controlcircuit, all according in aspects of the present invention;

FIG. 2 illustrates a reference voltage generator for supplying thereference voltage VR1 employed in the circuitry of FIG. 1;

FIG. 3 illustrates a reference voltage generator for supplying referencevoltages VR2 and VR3; and

FIG. 4 illustrates a low VCC protection circuit.

DETAILED DESCRIPTION

Referring to FIG. 1, column circuitry for a typical memory cell of thebi-stable flip-flop configuration is shown. Basically, FIG. 1 shows bitline load circuitry 10, a memory cell 12, bit lines 14 and 16 coupled toa column of memory cells, a word line 18 for a row, data write lines 20and 22, separate data read lines 24 and 26, and a column amplifier 40.The column includes plural memory cells, and there are plural suchcolumns with such circuitry in the memory, with the exception thatcurrent source loads are shared, as described infra.

Bit line circuits 10 in combination with memory cell 12 permit adifferential voltage to develop quickly on the bit lines 14 and 16 andpreserve cell stability by preventing the bit line voltages fromdropping too low. Also, circuits 10 (with the reference voltage VR1)provide high voltage gain independent of transistor characteristics.

In circuit 10, a clamp formed by transistor 30 cooperates with a currentsource formed by a P-channel transistor 32 and a reference voltage VR1.Transistor 30, which is N-channel, has its source coupled to bit line 14and its drain coupled to a source of operating voltage, in this case VCCwhich is 5.0 volts. The P-channel transistor 32 has its source coupledto VCC and its drain coupled to bit line 14. The gate of transistor 30is coupled to VCC. The gate of transistor 32 is coupled to the referencevoltage VR1 which is a variable voltage generated on chip. The circuitrywhich generates VR1 compensates for changes in both N-channeltransistors and P-channel transistors as occur in CMOS. This will bedescribed in connection with FIG. 2. However, VR1 is a DC voltage whichchanges value depending on ambient conditions. It tracks with thetransistor parameters and supplies a voltage to the gate of transistor32 so that the transistor provides a relatively constant current sourceto the bit line. Circuits 10, each having a current source and clamp,are provided for each of the two bit lines 14 and 16 in the illustratedembodiment.

The semiconductor industry generally does not use P-channel transistorsas a current source. Instead, it uses N-channel transistors or depletionmode transistors with each gate tied to the bit line. Such arrangementsprovide little clamping and do not track. The present arrangementcombines the features of bit line clamping together with tracking toprovide an improved device.

To read the memory cell 12, an equalizing signal is applied to turn on atransistor 34 whose source-drain path is coupled to the bit line pair 14and 16. This will equalize the bit lines at about 4.0 volts. .Iadd.Whenthe equilibrating clock signal turns off, transistor 34 is renderednon-conductive and voltage on the bit lines 14, 16 will depend on thememory cell 12 (when selected), the column amplifier, and the bit lineloads 10. The effect of the bit line loads will first be considered..Iaddend.At this time, with respect to the circuit 10, the P-channeltransistor 32 will be on, and the clamp formed by transistor 30 will notyet be on because transistor 30 is constructed so that its thresholdvoltage is about 1.5 volts. In this arrangement, then, transistor 30does not turn on until the bit line is about 1.5 volts below VCC. Thus,while the gate and drain of transistor 30 will be high, the transistorwill not turn on because the bit lines will have been equalized at about4 volts which does not provide an adequate low-voltage on the source oftransistor 30 to turn the transistor on. Thus, at this time, transistor32 provides a substantially constant current source relativelyindependent of bit line voltage. .[.The.]. .Iadd.Since each bit line 14,16 has a corresponding bit line load, as shown in FIG. 1, both of thebit lines will have a tendency to be pulled toward VCC by the action ofthe current sources, i.e. transistors 32. However, in the selected rowX_(n), the transistors 68, 70 are turn ON to couple the memory cell 12to bit lines 14, 16. Since the data stored in the memory cell is binary,one of the flip-flop transistors in the cell will be ON and will couplethe corresponding internal cell node, and consequently the correspondingbit line 14 or 16, to ground. As a result, the .Iaddend.memory cell 12will attempt to modulate the current on one of the bit lines..Iadd.Since device 32 is a P-channel transistor, when it is insaturation it acts as a constant current source, as is well known. Inthe saturation region, the current delivered to the drain of FET 32 willbe independent of the drain voltage and will be a function of the gateto source voltage of FET 32. Hence, under appropriate conditions asubstantially constant current flows through each FET 32 to itsrespective bit line. .Iaddend. Because the current source suppliesapproximately constant current, the bit line voltage must changegreatly. As the bit line changes, the difference in voltage between thebit lines 14 and 16 will be read. A delta of about 0.1 volts is enoughto read the cell. .[.When the equilibrating clock turns off, one of thebit lines.]. .Iadd.As previously mentioned, when the equilibratingsignal is turn OFF, transistor 34 is thereby rendered non-conductive andthe bit lines are no longer coupled to each other. One of the bit lines14, 16 .Iaddend. moves toward VCC as a result of its P-channeltransistor being on. The other bit line will move toward ground throughthe operation of the memory cell 12. As the voltage drops on the bitline toward ground, at some time there will be a voltage differentialsufficient for the clamp transistor 30 to turn on. This occurs at avoltage on the bit line of about 3.5 volts. The memory cell will pullthe bit line down to about 3 volts, but the clamp will prevent it fromdropping further. (Prior to this occurring the cell will have beenread.) By preventing the voltage on the bit lines from dropping too low,the danger of flipping memory cells is substantially reduced.

The lower portion of FIG. 1 illustrates the column read and writecircuitry. As can be seen, write lines 20 and 22 are separate from readlines 24 and 26. In this figure, the column select signal is Yn. When Ynis high, the column is selected to be read or written into. Adifferential column amplifier 40 is show including input transistors 42and 44, an N-channel transistor 46 which acts as a current source to thesources of input transistors 42 and 44, and P-channel transistors 48 and50 whose gates are both coupled to a second voltage reference VR2.Transistors 48 and 50 act as nearly ideal current source load providing,independent of read line voltage, a nearly constant current.

Transistors 52 and 54 are switching transistors acting as a controlcircuit. They switch the gate of transistor 46 between VR3 and grounddepending on the state of Yn. When Yn is low, the gate of transistor 46is low because of transistor 54 which turns on a path to ground. Also,when Yn is low, this turns on a transistor 56 which pulls a node 60 towithin one threshold voltage of VCC. Transistor 56 is a clamp transistorwhich holds node 60 at NCC minus Vtn when Yn is low.

While reading from the cell, the data write line 20 and its complement22 are held at VCC. The bit line voltages drive the column senseamplifier 40. This creates output signals on the data read lines 24 and26 which are sensed by a main read amplifier (not shown).

To write data into the memory cell 12, lines 20 or 22 are pulled to nearground by driver circuitry which pulls down a selected bit line viatransistors 62 or 64.

It will be noted that P-channel transistors 48 and 50 for the data readbuses 24 and 26 are to be shared by a number of columns each having acolumn amplifier arrangement as illustrated by transistors 42, 44, 46,52, 54 and 56.

FIG. 1 also includes a P-channel transistor 66 whose gate is coupled tothe column select signal Yn. This transistor is concerned with sneakpaths. In a large RAM, data read lines 24 and 26 will be coupled to thetransistors 42 and 44 of each column. Consider the columns other thanthe column containing the cell which is to be read. For each of thosenonselected columns, when the word line 18 for the addressed memory cellgoes high, it will couple not only the addressed cell to its bit lines,but also a plurality of adjacent memory cells to their corresponding bitlines. As a result, each column along the work line 18 will have a bitline 14 or 16 which will be at VCC. Bit lines 14 and 16 are connected tothe gates of their corresponding transistors 42 and 44. As a result, ineach nonselected column, the gate of a transistor 42 or 44 will be atVCC. Now, when the data read line 24 or 26 is lower than VCC minus Vth(where Vth represents a threshold voltage for an N-channel transistor),then a transistor 42 or 44 will turn on. This will occur in eachnonselected column. As a result, a data read line 24 or 26 would then becoupled to the nodes 60 in all of the nonselected columns, and thiswould increase the capacitive loading on the data read linessignificantly and reduce the speed of the RAM.

To overcome this problem, each column includes a transistor 66 whosesource-drain path selectively couples the bit lines 14 and 16. The gateof transistor 66 is coupled to the column select signal Yn, which ishigh when the column is selected. Transistor 66 is illustratively aP-channel device, so that when a column is selected (Yn is high), thetransistor 66 for the selected column will be off. However, thetransistors 66 in the nonselected columns will be on. Because suchmemory cell 12 along the active word line normally pulls down one of thebit lines 14 or 16 in its own column, when a transistor 66 is on in thatcolumn, such memory cell will pull down both of the bit lines below VCC.This keeps transistors 42 and 44 turned off in all of the nonselectedcolumns and eliminates the extra capacitance and problems associatedwith it.

The reference voltages of the preferred embodiment are generated bycircuits shown in FIGS. 2 and 3. Each of these circuits receives a chipselect signal CS. Also, each of these circuits includes both P channeland N channel transistors for modeling transistor characteristic changesin the circuitry of FIG. 1. The circuits of FIG. 1 through 4 are allconstructed on a single chip.

In FIG. 2, the chip select signal CS is coupled to a line 80. When CS islow, an output 81 of an inverter formed by transistors 90 and 92 ishigh. This will turn off P-channel transistors 84 and 86 and turn onN-channel transistor 88. The source-drain path of transistor 88 pulsenode 87 to ground. Node 87 is coupled to the gates of N-channeltransistor 96, 98 and 100 which therefore are turned off.

Further, when CS is low, P-channel transistor 82 is turned on to pullnode 83 to VCC. The source-drain path of transistor 82 pulls node 83 toVCC. Node 83 is coupled to the gate of a P-channel transistor 94 whichtherefore is turned off. It will be appreciated that transistors 94, 96,98 and 100 consume power and are therefore turn off when the chip selectsignal CS is low. When these transistors are off, P-channel transistor102 and N-channel transistors 104, 106 and 108 hold a node 85 .[.rear.]..Iadd.near .Iaddend.a voltage of about 3 volts (where VCC is 5 volts).Transistors 102 through 108 are small transistors and require low power.Node 85 provides the reference voltage VR1.

When the chip select signal goes high, transistor 82 is turned off. Theoutput 81 of the inverter formed by transistors 90 and 92 goes low sothat transistors 84 and 86 turn on and transistor 88 turns off. Nodes 83and 87 will then be connected to node 85. P-channel transistor 94 isturned on, and transistors 96, 98 and 100 will be turned on. Thisarrangement provides a self-biased inverter with the output node 85connected to input nodes 83 and 87. Output node 85 provides a referencevoltage .Iadd.VR1 .Iaddend.which tracks with the P-channel transistorcharacteristics which are molded by P-channel transistor 94. Further,the memory cell pass transistors 68 and 70 will be molded by transistors96, 98 and 100. Thus, the output VR1 tracks with changes in bothP-channel and N-channel transistors, and this allows biasing of the bitlines 14 and 16 independent of transistor characteristics. If P-channeltransistor 32 of FIG. 1 changes characteristics, transistor 94 will alsochange characteristics, it being on the same chip, and the load to thebit lines is compensated. The same is true for transistors 68 and 70vis-a-vis transistors 96 through 100.

Preferably, the reference voltage VR1 drives plural columns. In thepreferred embodiment, two generators, each as shown in FIG. 2, are usedfor a 64K CMOS static RAM.

FIG. 3 illustrates circuitry for providing reference voltages VR2 andVR3 for the column amplifier. The chip select signal in the generator ofFIG. 3 is applied to an inverter 114 comprising transistors 116 and 118.When the chip select signal is low, the output 120 of inverter 114 ishigh. Output 120 is applied to the gates of P-channel transistors andN-channel transistors in stages 110 and 112. Thus, when CS is low,P-channel transistor 128 is turned off and N-channel transistor 130 isturned on to pull a node 134 to ground via the source-drain path oftransistor 130. Node 134 provides the reference voltage VR2.Additionally, when the chip select signal CS is low, the current path ofVCC to ground in stage 110 through the source-drain paths of thetransistors 122, 124, 126, 128 and 130 is turned off.

When the chip select signal CS is high, the node 120 goes low whichturns on transistor 128 and turns off transistor 130. The voltage atnode 134 rises to a potential determined by the relative sizes oftransistors 122, 124, 126 and 128 relative to the size (width) ofN-channel transistor 132 whose gate is coupled to node 134. There willbe a current from VCC to ground in stage 110, therefore, when CS ishigh.

In stage 110, instead of using a single P-channel transistor formodeling the characteristics of P-channel transistors, multipleP-channel transistors 122, 124, 126 and 128 are used. This is to ensurethat they are each biased in the linear region, which minimizes thedrain to source voltage across each of those transistors. Transistors 48and 50 in FIG. 1 also are biased in the linear region. Thus, referencevoltage VR2 will track correctly with P-channel characteristics.

Stage 112 in FIG. 3 is the same as stage 110 except that it has oneP-channel transistor fewer. This is because reference voltage VR3 is ata higher potential than reference voltage VR2. This alleviates the needfor the extra transistor to ensure that they all stay in the linearregion.

In the preferred embodiment, VCC is 5 volts, reference voltage VR1 isabout 3 volts, reference voltage VR2 is about 1.7 volts, and referencevoltage VR3 is about 2.2 volts. This embodiment provides protectioncircuitry so that when VCC is below the expected 5 volt level, the partsshould still operate. Such protection circuit is shown in FIG. 4. Itincludes a circuit 134 cooperating with a P-channel transistor 136. WhenVCC drops, data read line 24 tends to drop too low because transistors48 and 50 becomes biased in the saturation region instead of the linearregion.

To safeguard against this, circuit 134 models a column amplifier 40. AsVCC lowers, a node 138 in circuit 134 drops low before the data readlines 24 and 26 drop low. Node 138 drops low before data read line 24drops low because the gate of a transistor 140 is driven by referencevoltage VR3 instead of VR2. This assures that transistor 140 enterssaturation before transistors 48 and 50 (FIG. 1) enter saturation as VCCdrops. When node 138 goes low, transistor 136 turns on to restrain line24 from dropping too low. If the supply voltage VCC were to drop to 3volts and the protection circuit of FIG. 4 was not used, then data readline 24 would crash to about 0.5 volts. However, by including theprotection circuit of FIG. 4, line 24 will be held to about 2 volts.

The present invention has been described in terms of a preferredembodiment which is illustrative. Other circuits are within the scope ofthe invention which is defined by the following claims.

I claim:
 1. In a CMOS integrated circuit device, a memory array andcontrol circuitry therefor comprising:a plurality of pairs of columnlines; a plurality of word lines; a plurality of multi-transistor memorycells, each cell including a pair of cross-coupled N-channel transistorsand being located at an intersection of, and connected to, a pair ofcolumn lines and one said word line; a plurality of bias .[.means.]..Iadd.circuite .Iaddend.each connected to a corresponding column line,each .[.said.]. bias .Iadd.circuit .Iaddend..].means.]. including aP-channel transistor and an N-channel transistor each having itssource-drain path coupled between a supply voltage and .[.said.]..Iadd.a .Iaddend.corresponding column line, each .[.said.]. bias.[.means serving to limit the current drain to the threshold level ofsaid P-channel transistor.]. .Iadd.circuit being arranged to limit thevoltage swing on the corresponding column line .Iaddend.as the.Iadd.corresponding .Iaddend.column line for the particular bias.[.means.]. .Iadd.circuit .Iaddend.is pulled toward ground; and avoltage reference circuit .[.connected.]. .Iadd.coupled .Iaddend.to saidsupply voltage .[.input.]. and having an output connected to the gatesof said P-channel transistors for each pair of .[.said.]. bias.[.means.]. .Iadd.circuits .Iaddend.connected to a pair of column lines,said reference circuit providing compensation means for reducing theeffects of .[.process variations between elements of said.]..Iadd.changes in the ambient conditions within the integrated circuit.Iaddend.device.
 2. The integrated circuit device of claim 1 whereineach said memory cell is a cross-coupled latch circuit comprised of fourN-channel transistors.
 3. The circuit of claim 1 wherein said voltagereference circuit includes a self-biased inverter including a P-channeltransistor and an N-channel transistor.
 4. In a CMOS integrated circuitdevice, a memory array and control circuitry therefor comprising:aplurality of pairs of column lines, each pair constituting a bit lineand a bit bar line; a plurality of work lines extending transverse tosaid pairs of column lines; a plurality of multi-transistor memorycells, each cell being located at an intersection of, and connected to,one word line and one pair of columns lines; a plurality of bias.[.means.]. .Iadd.circuits .Iaddend., each connected to one end of acorresponding column line, each .[.said.]. bias .[.means.]..Iadd.circuit .Iaddend.including a P-channel transistor and an N-channeltransistor, each .Iadd.of said transistors .Iaddend.having itssource-drain path connected between a supply voltage and .[.the.]..Iadd.a .Iaddend.corresponding column line, each .[.said.]. bias.[.means being operative for limiting the current drain to the thresholdlevel of said P-channel transistor.]. .Iadd.circuit being arranged tolimit the voltage swing on the corresponding column line .Iaddend.as thecorresponding column line for the particular bias .[.means.]..Iadd.circuit .Iaddend.is pulled toward ground; and a voltage referencecircuit having an output connected to the gates of the P-channeltransistors for the bias .[.means.]. .Iadd.circuits .Iaddend.for.[.column line pairs.]. .Iadd.said pairs of column lines .Iaddend., saidreference circuit having transistor elements sized to mirror transistorelements of said bias .[.means.]. .Iadd.circuits .Iaddend.and saidmemory cells and thereby compensate for .[.process variation withinsaid.]. .Iadd.changes in the ambient conditions within the integratedcircuit .Iaddend.device.
 5. The circuit device according to claim 4wherein said voltage reference circuit is comprised of a first P-channeltransistor having its drain connected to .Iadd.a .Iaddend.first .[.a.].source voltage and three N-channel transistors having their source drainpaths coupled in series between the source of said first P-channeltransistor and a reference potential.
 6. The column circuitry accordingto claim 4 wherein said voltage reference circuit includes P-channeltransistors and N-channel transistors to provide a first referencevoltage which varies to compensate for changes in the ambient conditionswithin the semi-conductor memory.
 7. In a semi-conductor memory havingat least two columns of memory cells for storing data, each columnhaving a pair of bit lines coupled to plurality of memory cells, saidmemory having a pair of data read lines and having address means forproviding a column select signal to each column, column circuitrycomprising:a respective differential amplifier for each of said columns,each said differential amplifier being coupled between said read linesand the pair of bit lines in the corresponding column, each differentialamplifier being responsive to an associated column select signal toprovide output signals on the read lines representative of the datastored in one of the memory cells in the corresponding columns when thecolumn is selected; and Sneak capacitance reduction means coupledbetween the pair of bit lines in each of columns and responsive to acolumn select signal for coupling together the pair of bit lines in acorresponding column when the corresponding column is not selected. 8.The column circuity according to claim 7 wherein said sneak capacitancereduction means includes, for each column, a transistor having itssource/drain path coupled between the bit lines in the correspondingcolumn and having its gate coupled to a select signal.
 9. In a CMOSintegrated circuit device, a memory array and control circuitry thereforcomprising:a plurality of pairs of bit lines; a plurality of word linesextending transverse to said pairs of bit lines; a plurality ofmulti-transistor memory cells, each cell including a pair ofcross-coupled transistors and being located at an intersection of, andconnected to, a corresponding pair of bit lines and a corrsponding wordline; a plurality of bias circuits coupled to said bit lines, each oneof said bit lines corresponding to a respective bias circuit, each.[.said.]. bias circuit including a P-channel transistor and .Iadd.an.Iaddend.N-channel transistor coupled to each other and coupled betweena supply voltage and the corresponding bit line, .[.said.]. .Iadd.each.Iaddend.bias circuit providing a clamp and a current source for the bitline corresponding to .[.the.]. .Iadd.that .Iaddend.bias circuit; and avoltage reference circuit coupled to said supply voltage and having anoutput coupled to the gate electrodes of said P-channel transistors insaid plurality of bias circuits, said reference circuit reducing theeffects of .[.process variations between elements of said.]..Iadd.changes in the ambient conditions within the integrateed circuit.Iaddend.device.
 10. The integrated circuit device of claim 9 whereineach said memory cell comprises a cross-coupled latch circuit havingfour N-channel transistors.
 11. The integrated circuit device of claim9, said reference circuit having elements sized to track .[.the.].effects .[.of.]. .Iadd.on .Iaddend.transistor elements of the pluralityof bias circuits and said memory cells and thereby compensate for.[.process variations within said.]. .Iadd.changes in the ambientconditions within the integrated circuit.Iaddend.device.
 12. The circuitdevice according to claim 9 wherein said voltage reference circuitcomprises a first P-channel transistor having its source-drain coupledbetween a first source voltage and said output of said voltage referencecircuit, and further comprises three N-channel transistors having theirsource-drain paths coupled in series between a reference potential andsaid ouptut.
 13. The circuit of claim 9 wherein said voltage referencecircuit includes a self-biased inverter including a P-channel transistorand an N-channel transistor.
 14. The column circuitry of claim 9 whereinsaid voltage reference circuit provides a non-zero voltage to the gateelectrodes of said P-channel transistors in said plurality of biascircuits.
 15. The column circuitry of claim 9 wherein saidsemi-conductor memory includes a pair of data read lines coupled to aplurality of pairs of input transistors each gated by a correspondingbit line and each selectively coupling a respective data read line to acommon node between an associated pair of input transistors, wherebyeach column comprises a pair of bit lines and has associated with it arespective common node selectively coupled to the data read lines; thecolumn circuitry further comprising a current source load coupled tosaid data read lines and to a second voltage reference circuit whichprovides a second reference voltage which varies to compensate forchanges in the ambient conditions within the semi-conductor memory. 16.The memory according to claim 15 further comprising a plurality of sneakcapacitance reduction means each coupled between a respective pair ofsaid bit lines and being responsive to a column select signal to couplethe bit line pair together to permit the memory cell therebetween toisolate said read lines from each of said common nodes except for thecommon node in the selected column.